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1. general description the tdf8599a is a dual bridge-tied load (btl) car audio amplifier comprising an ndmost-ndmost output stage based on soi bcdmos technology. low power dissipation enables the tdf8599a high-efficiency, class-d amplifier to be used with a smaller heat sink than those normally used with standard class-ab amplifiers. the tdf8599a can operate in either non-i 2 c-bus mode or i 2 c-bus mode. when in i 2 c-bus mode, dc load detection results and faul t conditions can be easily read back from the device. up to 15 i 2 c-bus addresses can be selected depending on the value of the external resistor connected to pins ads and mod. when pin ads is short circuited to ground, the tdf8599a operates in non-i 2 c-bus mode. switching between operating mode and mute mode in non-i 2 c-bus mode is only possible using pins en and sel_mute. 2. features and benefits ? high-efficiency ? low quiescent current ? operating voltage from 8 v to 35 v ? two 4 ? /2 ? capable btl channels or one 1 ? capable btl channel ? differential inputs ? i 2 c-bus mode with 15 i 2 c-bus addresses or non-i 2 c-bus mode operation ? clip detect ? independent short circuit protection for each channel ? advanced short circuit protection for load, gnd and supply ? load dump protection ? thermal foldback and thermal protection ? dc offset protection ? selectable ad or bd modulation ? parallel channel mode for hi gh current drive capability ? advanced clocking: ? switchable oscillator clock source: internal for master mode or external for slave mode ? spread spectrum mode ? phase staggering ? frequency hopping ? no ?pop noise? caused by dc output offset voltage tdf8599a i 2 c-bus controlled dual channel 135 w/4 ? , single channel 250 w/2 ? class-d power amplifie r with load diagnostics rev. 3 ? 2 may 2013 product data sheet
tdf8599a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 2 may 2013 2 of 55 nxp semiconductors tdf8599a i 2 c-bus controlled dual channel class-d power amplifier ? i 2 c-bus mode: ? dc load detection ? ac load detection ? thermal pre-warning diagnostic level setting ? identification of activated protections or warnings ? selectable diagnostic information available using pins diag and clip ? qualified in accordance with aec-q100 3. applications ? car audio 4. quick reference data [1] in this data sheet supply voltage v p describes v p1 , v p2 and v pa . [2] output power is measured indirectly based on r dson measurement. 5. ordering information table 1. quick reference data v p = 14.4 v unless otherwise stated. symbol parameter conditions min typ max unit v p supply voltage [1] 8 14.4 35 v i p supply current off state; t j ? 85 ?c; v p =14.4v - 2 10 ? a i q(tot) total quiescent current operating mode; no load, snubbers and filter connected -90120ma p o output power stereo mode: [2] v p =14.4v; thd=1%; r l =4 ? 18 20 - w v p = 14.4 v; thd = 10 %; r l =4 ? 23 25 - w square wave (eiaj); r l =4 ? -40-w v p = 35 v; thd = 10 %; r l =4 ? - 135 - w v p =14.4v; thd=1%; r l =2 ? 26 29 - w v p = 14.4 v; thd = 10 %; r l =2 ? 34 38 - w square wave (eiaj); r l =2 ? -60-w parallel mode: [2] v p = 14.4 v; thd = 10 %; r l =2 ? -50-w v p = 35 v; thd = 10 %; r l =2 ? - 250 - w v p =25v; thd=1%; r l =1 ? 135 150 - w table 2. ordering information type number package name description version tdf8599ath hsop36 plastic, heatsink small outline package; 36 leads; low stand-off height sot851-2
tdf8599a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 2 may 2013 3 of 55 nxp semiconductors tdf8599a i 2 c-bus controlled dual channel class-d power amplifier 6. block diagram fig 1. block diagram 001aak071 pwm control tdf8599a driver high stabi1 5 v stabi stabi2 v p1 out1n boot1p out1p out2n boot2p out2p vstab2 33 vstab1 34 24 31 10 9 1 2 5 3 4 8 agnd svrr in1p in1n acgnd in2p in2n v p2 v p1 v dda 32 29 28 23 22 26 27 pgnd1 v p1 pgnd1 + driver low pwm control driver high driver low boot1n boot2n pwm control driver high v p2 pgnd2 v p2 pgnd2 driver low pwm control driver high driver low oscillator 18 oscset 19 oscio 17 ssm 12 mod mode select + i 2 c-bus diagnostics protection ovp, ocp, otp uvp, tfp, wp, dcp gndd/hw clip dcp 6 en 7 sel_mute 16 scl 15 sda 11 36 diag 14 13 20 ads pgnd1 30 pgnd2 25 35 v ddd 21
tdf8599a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 2 may 2013 4 of 55 nxp semiconductors tdf8599a i 2 c-bus controlled dual channel class-d power amplifier 7. pinning information 7.1 pinning 7.2 pin description fig 2. heatsink up (top view) pin configuration tdf8599ath tdf8599ath out1n in1p boot1n in1n v p1 in2p pgnd1 gndd/hw v ddd vstab1 in2n boot1p acgnd out1p en out2p sel_mute boot2p svrr pgnd2 agnd v p2 v dda ads mod 001aak072 36 35 34 33 32 31 30 29 28 27 26 25 11 12 9 10 7 8 clip boot2n diag out2n sda vstab2 scl 24 23 22 21 15 16 13 14 dcp ssm oscio oscset 20 19 17 18 5 6 3 4 1 2 table 3. pin description symbol pin type [1] description in1p 1 i channel 1 positive audio input in1n 2 i channel 1 negative audio input in2p 3 i channel 2 positive audio input in2n 4 i channel 2 negative audio input acgnd 5 i decoupling for input reference voltage en 6 i enable input: non-i 2 c-bus mode: switch between off and mute mode i 2 c-bus mode: off and standby mode sel_mute 7 i select mute or unmute svrr 8 i decoupling for internal half supply reference voltage agnd 9 g analog supply ground v dda 10 p analog supply voltage ads 11 i non-i 2 c-bus mode: connected to ground i 2 c-bus mode: selection and address selection pin mod 12 i modulation mode, phase shift and parallel mode select
tdf8599a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 2 may 2013 5 of 55 nxp semiconductors tdf8599a i 2 c-bus controlled dual channel class-d power amplifier [1] i = input, o = output, i/o = input/output, g = ground and p = power supply. [2] in this data sheet supply voltage v p describes v p1 , v p2 and v pa . 8. functional description 8.1 general the tdf8599a is a dual full bridge (btl) audi o power amplifier usi ng class-d technology. the audio input signal is converted into a pu lse-width modulated (pwm) signal using the analog input and pwm control stages. a pwm signal is applied to driver circuits for both high-side and low-side enabling the dmos po wer output transistors to be driven. an external 2 nd order low-pass filter converts the pwm signal into an analog audio signal across the loudspeakers. clip 13 o clip output; open-drain diag 14 o diagnostic output; open-drain sda 15 i/o i 2 c-bus data input and output scl 16 i i 2 c-bus clock input ssm 17 master setting: spread spectrum mode frequency slave setting: phase lock operation oscset 18 master/slave oscillator setting master only setting: set internal oscillator frequency oscio 19 i/o external oscillator slave setting: input internal oscillator master setting: output dcp 20 i dc protection input for the filtered output voltages vstab2 21 decoupling internal stabilizer 2 for dmost drivers out2n 22 o channel 2 negative pwm output boot2n 23 boot 2 negative bootstrap capacitor v p2 [2] 24 p channel 2 power supply voltage pgnd2 25 g channel 2 power ground boot2p 26 boot 2 positiv e bootstrap capacitor out2p 27 o channel 2 positive pwm output out1p 28 o channel 1 positive pwm output boot1p 29 boot 1 positiv e bootstrap capacitor pgnd1 30 g channel 1 power ground v p1 [2] 31 p channel 1 power supply voltage boot1n 32 boot 1 negative bootstrap capacitor out1n 33 o channel 1 negative pwm output vstab1 34 decoupling internal stabilizer 1 for dmost drivers v ddd 35 decoupling of the internal 5 v logic supply gndd/hw 36 g ground digital supply voltage handle wafer connection table 3. pin description ?continued symbol pin type [1] description
tdf8599a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 2 may 2013 6 of 55 nxp semiconductors tdf8599a i 2 c-bus controlled dual channel class-d power amplifier the tdf8599a includes integrat ed common circuits for all chann els such as the oscillator, all reference sources, mode functionality and a digital timing manager. in addition, the built-in protection includes thermal foldback , temperature, overcurrent and overvoltage (load dump). the tdf8599a operates in either i 2 c-bus mode or non-i 2 c-bus mode. in i 2 c-bus mode, dc load detection, frequency hopping and exte nded configuration functions are provided together with enhanced diagnostic information. 8.2 mode selection the mode pins en, ads and sel_mute enable mute state, i 2 c-bus mode and operating mode switching. pin sel_mute is used to mute and unmute the device and must be connected to an external capacitor (c on ). this capacitor generates a ti me constant which is used to ensure smooth fade-in and fade-out of the input signal. the tdf8599a is enabled when pin en is hi gh. when pin en is low, the tdf8599a is off and the supply current is at its lowest value (typically 2 ? a). when off, the tdf8599a is completely deactivated and will not react to i 2 c-bus commands. i 2 c-bus mode is selected by connecting a resistor between pins ads and agnd. in i 2 c-bus mode with pin en high, the tdf8599a waits for further commands (see ta b l e 4 ). i 2 c-bus mode is described in section 9 on page 23 . non-i 2 c-bus mode is selected by connecting pin ads to pin agnd. in non-i 2 c-bus mode, the default tdf8599a state is mute mode. the amplifiers switch idle (50 % duty cycle) and the audio signal is suppressed at th e output. in addition, the capacitor (c svrr ) is charged to half the supply voltage. to enter operating mode, pin sel_mute must be hgh with s1 open, enabling capacitor (c on ) charged by an internal pull-up (see figure 3 ). in addition, pin en must be driven high. i 2 c-bus mode and non-i 2 c-bus mode control are described in table 4 on page 7 and table 5 on page 7 . switches s1 and s2 are shown in figure 3 . a. non-i 2 c-bus mode b. i 2 c-bus mode see ta b l e 1 3 for detailed information on r ads . fig 3. mode selection 001aak073 sel_mute en 3.3 v c on s1 s2 tdf8599a ads agnd 001aak074 sel_mute en 3.3 v c on s2 tdf8599a ads r ads agnd
tdf8599a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 2 may 2013 7 of 55 nxp semiconductors tdf8599a i 2 c-bus controlled dual channel class-d power amplifier [1] x = do not care. [1] x = do not care. 8.3 pulse-width modul ation frequency the output signal from the amplifier is a pwm signal with a clock frequency of f osc . this frequency is set by co nnecting a resistor (r osc ) between pins oscset and agnd. the optimal clock frequency setting is between 300 khz and 400 khz. connecting a resistor with a value of 39 k ? , for example, sets the clock frequency to 320 khz (see figure 5 ). the external capacitor (c osc ) has no influence on the os cillator frequency. it does however, reduce jitter and sensitivity to disturbance. using a 2 nd order lc demodulation filter in the application generates an anal og audio signal across the loudspeaker. 8.3.1 master and slave mode selection in a master and slave configuration, multiple tdf8599a devices are daisy-chained together in one audio application with a single device providing the clock frequency signal for all other devices. in this si tuation, it is recomm ended that the oscilla tors of all devices are synchronized for optimum emi behavior as follows: all oscio pins are connected together and one tdf8599a in the application is configured as the clock-master. all other tdf8599a devices are configured as clock-slaves (see figure 5 ). ? the clock-master pin oscio is configured as the oscillato r output. when a resistor (r osc ) is connected between pins oscset and agnd, the tdf8599a is in master mode. ? the clock-slave pins oscio are configur ed as the oscillator inputs. when pin oscset is directly connected to pin agnd (see table 6 ), the tdf8599a is in slave mode. table 4. i 2 c-bus mode operation pin en pin sel_mute bit ib1[d0] bit ib2[d0] mode high (s2 closed) high 1 0 operating mode low 1 1 mute mode low 0 x [1] standby mode low (s2 open) x [1] x [1] x [1] off (default) table 5. non-i 2 c-bus mode operation pin en pin sel_mute mode high (s2 closed) high (s1 open) operating mode low (s1 closed) m ute mode (default) low (s2 open) x [1] off table 6. mode setting pin oscio mode settings pin oscset pin oscio master r osc > 26 k ? output slave r osc =0 ? ; shorted to pin agnd input
tdf8599a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 2 may 2013 8 of 55 nxp semiconductors tdf8599a i 2 c-bus controlled dual channel class-d power amplifier the value of the resistor r osc sets the clock frequency based on equation 1 : (1) in master mode, spread spectrum mode and frequency hopping can be enabled. in slave mode, phase staggering and phase lock operation can be selected. an external clock can be used as the master-clock on pin oscio of the slave devices. when using an external clock, it must remain active during the shutdown sequence to ensure that all devices are switched off and able to enter the off state as described in section 8.2 on page 6 . in slave mode, an internal watchdog timer on pin oscio is triggered when the tdf8599a is switched off by pulling down pin en. if the ex ternal clock fails, the watchdog timer forces the tdf8599a to switch off. 8.3.2 spread spectrum mode (master mode) spread spectrum mode is a technique of modulating the oscillator frequency with a slowly varying signal to broaden the switching spectrum, thereby reducing the spectral density of the emi. connecting a capacitor (c ssm ) to pin ssm enables spread spectrum mode (see figure 6 ). when pin ssm is connected to pin agnd, spread spectrum mode is disabled. fig 4. clock frequency as a function of r osc fig 5. master and slave configuration f osc 12.45 10 9 ? r osc --------------------------- - hz ?? = 001aai771 f osc (khz) 300 500 450 350 400 20 30 10 40 50 r osc (k) 0 001aak075 oscset oscio master c osc r f osc r osc tdf8599a oscset oscio slave 1 tdf8599a oscset oscio slave 2 tdf8599a
tdf8599a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 2 may 2013 9 of 55 nxp semiconductors tdf8599a i 2 c-bus controlled dual channel class-d power amplifier the capacitor on pin ssm (c ssm ) sets the spreading frequency when spread spectrum mode is active. the current (i ssm ) flowing in and out of pin ssm is typically 5 ? a. this gives a triangular voltage on pin ssm that sweeps around the voltage set by pin oscset ? 5 %. the voltage on pin ssm is used to modulate the os cillator frequency. the spread spectrum frequency (f ssm ) can be calculated using equation 2 : (2) where the voltage on pin oscset = v 1 and is calculated as 100 ? a ? r osc (v) with i ssm =5 ? a. the frequency swings between 0.95 ? f osc and 1.05 ? f osc ; see figure 7 . 8.3.3 frequency hopping (master mode) frequency hopping is a techni que used to change the osc illator frequency for am tuner compatibility. in master mode, the resistor connected betw een pins oscset and agnd sets the oscillator frequency (f osc ). in i 2 c-bus mode, this frequency can be varied by ? 10 %. set bit ib1[d4] to logic 1 and bit ib1[d3] to either logic 0 (0.9 ? f osc ) or logic 1 (1.1 ? f osc ). f ssm i ssm 2c ssm ? v 1 ? 10 % ? ----------------------------------------------------- hz ?? = a. off b. on fig 6. spread spectrum mode 001aai773 100 a r osc ssm c osc oscset 001aai774 100 a 5 a i ssm r osc ssm c osc c ssm oscset fig 7. spread spectrum operation in master mode 001aai775 t (ms) oscio max(v) min(v) ssm
tdf8599a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 2 may 2013 10 of 55 nxp semiconductors tdf8599a i 2 c-bus controlled dual channel class-d power amplifier 8.3.4 phase lock operation (slave mode) in slave mode, phase-locked loop (pll) operation can be used to reduce the jitter effect of the external oscillator sign al connected to pin oscio. phase lock operation is also needed to enable phase staggering, see section 8.4.2 on page 13 . phase lock operation is enabled when the oscillator is in slav e mode by connecting two capacitors (c pll_s and c pll_p ) and a resistor (r pll ) between pin ssm and pin agnd (see figure 8 ). connecting pin ssm to pin agnd disables phase lock oper ation and causes the slave to directly use the external oscillator signal. values for c pll_s , c pll_p and r pll depend on the desired loop bandwidth (b pll ) of the pll. r pll is given by: r pll =8.4 ? b pll ? . the corresponding values for c pll_s and c pll_p are given by equation 3 and equation 4 : (3) remark: c pll_p is only needed when 1 4 ? phase shift is selected. see section 8.4.2 for more detailed information. (4) when pin oscio is connected to a clock- master with spread spectrum mode enabled, the pll loop bandwidth b pll should be 100 ? f ssm . ta b l e 7 lists all oscillator modes. (1) only needed when 1 4 ? phase shift is selected a. off b. on fig 8. phase lock operation table 7. oscillator modes oscset pin oscio pin ssm pin oscillator modes r osc > 26 k ? output c ssm to pin agnd master, spread spectrum r osc > 26 k ? output shorted to pin agnd master, no spread spectrum r osc =0 ? input c pll + r pll to pin agnd slave, pll enabled r osc =0 ? input shorted to pin agnd slave, pll disabled c pll_p 0.032 r pll b pll ? ------------------------------ f ?? c pll_s 0.8 r pll b pll ? ------------------------------ f ?? 001aai776 100 a ssm oscset pll 001aai777 100 a pll oscset r pll c pll_p (1) c pll_s ssm
tdf8599a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 2 may 2013 11 of 55 nxp semiconductors tdf8599a i 2 c-bus controlled dual channel class-d power amplifier 8.4 operation mode selection pin mod is used to select specific operating modes. the resistor (r mod ) connected between pins mod and agnd together with the non-i 2 c-bus/i 2 c-bus mode determine the operating mode (see ta b l e 8 ). the mode of operation depends on whether non-i 2 c-bus mode or i 2 c-bus mode is active. this in turn is de termined by the resistor value connected between pins ads and agnd. in non-i 2 c-bus mode, pin mod is used to select: ? ad or bd modulation (see section 8.4.1 ). ? 1 2 ? phase shift when oscillator is used in slave mode (see section 8.4.2 ). ? parallel mode operation (see section 8.4.3 ). in i 2 c-bus mode, pin mod can only select para llel mode. in additio n, the modulation mode and phase shift are programmed using i 2 c-bus commands. [1] r ads ? 4.7 k ? ; see table 13 on page 23 . [2] r ads = 0 ? ; pin ads is short circuited to pin agnd. [3] see section 8.4.3 on page 14 for more detailed information. in i 2 c-bus mode, pin mod is latched using the i 2 c-bus command ib3[d7] = 1. this avoids amplifier switching interf erence generating incorrect information on pin mod. in non-i 2 c-bus mode or when ib3[d7] = 0, the information on pin mod is latched when one of the tdf8599a?s outputs starts switching. 8.4.1 modulation mode in non-i 2 c-bus mode, pin mod is used to select either ad or bd modulation mode (see ta b l e 8 ). in i 2 c-bus mode, the modulation mode is selected using an i 2 c-bus command. ? ad modulation mode: the bridge halves switch in opposite phase. ? bd modulation mode: the bridge halves swit ch in phase but the input signal for the modulators is inverted. figure 10 and figure 11 show simplified representations of ad and bd modulation. table 8. operation mode selection with the mod pin r mod (k ? ) i 2 c-bus mode [1] non-i 2 c-bus mode [2] 0 (short to agnd) stereo mode ad modulation: no phase shift in slave mode 4.7 bd modulation: no phase shift in slave mode 13 ad modulation: 1 2 ? phase shift in slave mode 33 parallel mode [3] bd modulation: 1 2 ? phase shift in slave mode 100 ad modulation: no phase shift in slave mode ? (open) bd modulation: no phase shift in slave mode
tdf8599a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 2 may 2013 12 of 55 nxp semiconductors tdf8599a i 2 c-bus controlled dual channel class-d power amplifier fig 9. ad/bd modulation switching circuit a. bridge half 1. b. bridge half 2 switched in the opposite phase to bridge half 1. fig 10. ad modulation 001aai778 +v p outp ad bd inxp inxn outn +v p 001aai779 inxp outxp 001aai780 inxn outxn
tdf8599a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 2 may 2013 13 of 55 nxp semiconductors tdf8599a i 2 c-bus controlled dual channel class-d power amplifier 8.4.2 phase staggering (slave mode) in slave mode with phase lock operation e nabled, a phase shift with respect to the incoming clock signal can be selected to dist ribute the switching moments over time. in non-i 2 c-bus mode, 1 2 ? phase shift can be programmed using pin mod. in i 2 c-bus mode, five different phase shifts ( 1 4 ? , 1 3 ? , 1 2 ? , 2 3 ? , 3 4 ? ) can be selected using the i 2 c-bus bits (ib3[d1:d3]). see ta b l e 8 for selection of the phase shift in non-i 2 c-bus mode with pin mod. an additional capacitor must be connected to pin ssm when 1 4 ? phase shift is used (see figure 8 ). an example of using 1 2 ? phase shift for bd modulation is shown in figure 12 . a. phase switching cycle. b. inverted signal to the modulator. fig 11. bd modulation 001aai781 inxp outxp outxp - outxn 001aai782 inxn outxn
tdf8599a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 2 may 2013 14 of 55 nxp semiconductors tdf8599a i 2 c-bus controlled dual channel class-d power amplifier 8.4.3 parallel mode in parallel mode; the tw o output stages operate in parallel to enlarge the dr ive capability. the inputs and outputs for parallel mode must be connected on the printed-circuit board (pcb) as shown in figure 13 . the parallel connection can be made after the output filter, as shown in figure 13 or directly to the device output pins (outxp and outxn). in parallel mode, the channel 1 i 2 c-bus bits can be programmed using the i 2 c-bus. 8.5 protection the tdf8599a includes a range of built-i n protection functions. how the tdf8599a manages the various possible fault conditions for each protection is described in the following sections: fig 12. master and slave operation with 1 2 ? phase shift 001aai783 out1p phase 0 out1n out2p out2n out1p out1n out2p master slave out2n 1 2 2 3 fig 13. parallel mode 001aak077 in1p mod r mod in2n in1n out1n out2n out1p out2p + ? ? + in2p tdf8599a
tdf8599a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 2 may 2013 15 of 55 nxp semiconductors tdf8599a i 2 c-bus controlled dual channel class-d power amplifier 8.5.1 thermal foldback thermal foldback protection (tfp) is tripped when the average junction temperature exceeds the threshold level (145 ? c). tfp decreases amplifier gain such that the combination of power dissipation and r th(j-a) create a junction temperature around the threshold level. the de vice will not completely switch of f but remains operational at the lower output power levels. if the average junction temperature continues to increase, a second built-in temperature protection threshold level shuts down the amplifier completely. 8.5.2 overtemperature protection if the average junction temperature (t j ) > 160 ? c, overtemperature pr otection (otp) is tripped and the power stage shuts down immediately. 8.5.3 overcurrent protection overcurrent protection (ocp) is tripped w hen the output current exceeds the maximum output current of 8 a. ocp regulates the out put voltage such that the maximum output current is limited to 8 a. the amplifier outputs ke ep switching and th e amplifier is not shutdown completely. this is called current limiting. ocp also detects when the loudspeaker terminals are short circuited or one of the amplifier?s demodulated outputs is short circuited to one of the supply lines. in either case, the shorted channel(s) are switched off. the amplifier can distinguish between loudspeaker impedance drops and a low-ohmic short across the load or one of the supply lines. this impedance threshold depends on the supply voltage used. when a short is made across the load causing the impedance to drop below the threshold level, the shorted ch annel(s) are switched off. they try to restart every 50 ms. if the short circuit condition is still present after 50 ms, the cycle repeats. the average power dissipation will be low beca use of this reduced duty cycle. when a channel is switched off due to a sh ort circuit on one of the supply lines, window protection (wp) is activated. wp ensures the amplifier does not start-up after 50 ms until the supply line short circuit is removed. 8.5.4 window protection window protection (wp) chec ks the pwm output voltage before switching from standby mode to mute mode (with both outputs switching) and is activated as follows: table 9. overview of protection types protection type reference thermal foldback section 8.5.1 overtemperature section 8.5.2 overcurrent section 8.5.3 window section 8.5.4 dc offset section 8.5.5 undervoltage section 8.5.6 overvoltage section 8.5.6
tdf8599a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 2 may 2013 16 of 55 nxp semiconductors tdf8599a i 2 c-bus controlled dual channel class-d power amplifier ? during the start-up sequence: ? when the tdf8599a is switched from standby to mute (t d(stb-mute) ). when a short circuit on one of the output terminals (i.e. between v p or gnd) is detected, the start-up procedure is interrupted and the tdf8599a waits for open circuit outputs. no large currents flow in the event of a sh ort circuit to the supply lines because the check is performed before the power stages are enabled. ? during operation: ? a short to one of the supply lines trips ocp causing the amplifier channel to shutdown. after 50 ms the amplifier channel restarts and wp is activated. however, the corresponding amplifier chann el will not start-up un til the supply line short circuit has been removed. 8.5.5 dc offset protection dc protection (dcp) is activated when the dc content in the demodulated output voltage exceeds a set threshold (typically 2 v). dcp is active in both mute mode and operating mode. figure 14 shows how false triggering of the dcp by low frequencies in the audio signal is prevented using the external capacitor (c f ) to generate a cut-off frequency. in i 2 c-bus mode, dc offsets generate a voltage shift around the bias voltage. when the voltage shift exceeds threshold values, the of fset alarm bit db1[d2] is set and if bit ib1[d7] is not set, diagnostic information is also given. any detected offset shuts down both channels when bit ib2[d7] is not set. to restart the tdf8599a in i 2 c-bus mode, pin en must be toggled or dcp disabled by connecting pin dcp to pin agnd. fig 14. dc offset protection and diagnostic output 001aak078 out1p out1n v to i out2p out2n dcp diag switch off channels ib1[d6] ib2[d6] v to i v ref sq db1[d2] ib1[d7] ib2[d7] s4 50 k s3 c f
tdf8599a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 2 may 2013 17 of 55 nxp semiconductors tdf8599a i 2 c-bus controlled dual channel class-d power amplifier in non-i 2 c-bus mode, when an offset is detected, dcp always gives diagnostic information on pin diag and shuts down both channels. connecting a capacitor between pins dcp and agnd enables dc offset protection. connecting pin dcp to pin agnd disables dcp in both i 2 c-bus and non-i 2 c-bus mode. 8.5.6 supply voltages undervoltage protection (uvp) is activated when the supply voltage drops below the uvp threshold. uvp triggers the uvp circuit causin g the system to first mute and then stop switching. when the supply voltage rises above the threshold level, the system restarts. overvoltage protection (ovp) is activate d when the supply voltage exceeds the ovp threshold. the ovp (or load dump) circuit is activated and the power stages are shutdown. an overview of all protection circuits and the amplifier states is given in ta b l e 1 0 . 8.5.7 overview of protection circuits and amplifier states [1] when fault is removed. [2] amplifier gain depends on the junction temperature and size of the heat sink. [3] tfp influences restart timi ng depending on heat sink size. [4] shorted load causes a restart of the channel every 50 ms. [5] latched protection is reset by toggling pin en or by disabling dcp in i 2 c-bus mode. [6] in i 2 c-bus mode deep supply voltage drops will cause a power-on reset (por). the restart requires an i 2 c-bus command. 8.6 diagnostic output 8.6.1 diagnostic table the diagnostic information for i 2 c-bus mode and non-i 2 c-bus mode is shown in table 11 . the instruction bitmap and data bytes are described in ta b l e 1 4 and table 15 . pins diag and clip have an open-drain output which must have an external pull-up resistor connected to an external voltage. pins clip and diag can show both fixed and i 2 c-bus selectable information. table 10. overview of tdf8599a protec tion circuits and amplifier states protection circuit name amplifier state complete shutdown channel shutdown restart [1] tfp n [2] n [2] y [3] otp y n y [3] ocp n y y [4] wp n y y dcp y n n [5] uvp y n y [6] ovp y n y
tdf8599a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 2 may 2013 18 of 55 nxp semiconductors tdf8599a i 2 c-bus controlled dual channel class-d power amplifier pin diag goes low when a short circuit to one of the amplifier outputs occurs. the microprocessor reads the failure information using the i 2 c-bus. the i 2 c-bus bits are set for a short circuit. these bits can be reset with the i 2 c-bus read command. even after the short has been removed, the microprocessor knows what was wrong after reading the i 2 c-bus. old information is read when a single i 2 c-bus read command is used. to read the current information, two read commands must be sent, one after another. when selected, pin diag gives the current dia gnostic information. pi n diag is released instantly when the failure is removed, independent of the i 2 c-bus latches. when ocp is triggered, the op en-drain diag output is acti vated. the diagnostic output signal during different short circ uit conditions is illustrated in figure 15 . 8.6.2 load identification (i 2 c-bus mode only) 8.6.2.1 dc load detection dc load detection is only available in i 2 c-bus mode and is controlled using bit ib2[d2]. the default setting is logic 0 for bit ib2[d2] which disables dc load detection. dc load detection is enabled when bit ib2[d2] = 1. load detection takes place before the class-d amplifier output stage starts switching in mute mode and the start-up time from standby mode to mute mode is increased by t det(dcload) (see figure 16 ). table 11. available data on pins diag and clip diagnostic i 2 c-bus mode non-i 2 c-bus mode pin diag pin clip pin diag pin clip power-on reset yes yes yes yes uvp or ovp yes no yes no clip detection no selectable no yes temperature pre-warning no selectable no yes ocp/wp yes no yes no dcp selectable no yes no otp yes no yes no fig 15. diagnostic output for short circuit conditions 001aai786 amplifier restart shorted load pull up v agnd = 0 v 50 ms 50 ms 50 ms no restart short to gnd or v p line
tdf8599a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 2 may 2013 19 of 55 nxp semiconductors tdf8599a i 2 c-bus controlled dual channel class-d power amplifier the capacitor connected to pin sel_mute (see figure 3 on page 6 ) is used to create an inaudible current test pulse, drawn from the positive amplifier output. the diagnostic ?speaker load? (or ?open load?), based on th e voltage difference between pins outxp and outxn is shown in figure 18 . remark: dc load detection identifies a short circuited speaker as a valid speaker load. ocp detection, using byte db1[d3] for channel 1 and byte db2[d3] for channel 2, performs diagnostics on shorted loads. howe ver, the diagnostics are performed after the dc load detection cycle has finished and once the amplifier is in operating mode. the result of the dc load detection is stored in bits db1[d4] and db2[d4]. fig 16. dc load detection circuit fig 17. dc load detection procedure fig 18. dc load detection limits 001aai787 pwm control driver high v p pgnd1 outn outp r l b driver low pwm control driver high v p pgnd2 driver low 001aai788 out (v) t det(dcload) t d(stb-mute) t (s) out? out+ 001aaj956 0 25 350 speaker load open load
tdf8599a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 2 may 2013 20 of 55 nxp semiconductors tdf8599a i 2 c-bus controlled dual channel class-d power amplifier remark: after dc load detection has been performed, the dc load valid bit db1[d6] must be set. the dc load data bits are only valid when bit db1[d6] = 1. when dc load detection is interrupted by a sudden large change in supply voltage (triggered by uvp or ovp) or if the amplifier hangs up, the dc load valid bit is reset to db1[d6] = 0. the dc load detection enable bit ib2[d2] must be reset after the dc load protection cycle to release any amplifier hang-up. once the dc load detection cycle has finished, dc load detection can be restarted by toggling the dc load detection enable bit ib2[d2]. however, this can only be used if both amplifier c hannels have not been enabled with bit ib1[d1] or bit ib2[d1]. see section 8.6.2.2 ? recommended start-up sequence with dc load detection enabled ? for detailed information. 8.6.2.2 recommended start-up sequence with dc load detection enabled the flow diagram ( figure 19 ) illustrates the tdf8599a?s ability to perform a dc load detection without starting the amplifiers. afte r a dc load detection cycle finishes without setting the dc load valid bit db1[d6], dc load de tection is repeated (when bit ib2[d2] is toggled). to limit the maximum number of dc load detection cycle loops, a counter and limit have been added. the loop exits after the predefined number of cycles (countmax), if the dc load detection cycle finishes with an invalid detection. depending on the application needs, the invalid dc load detection cycle can be handled as follows: ? the amplifier can be started without dc load detection ? the dc load detection loop can be executed again table 12. interpretation of dc load detection bits dc load bits db1[d4] and db2[d4] ocp bits db1[d3] and db2[d3] description 0 0 speaker load 0 1 shorted load 1 0 open load
tdf8599a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 2 may 2013 21 of 55 nxp semiconductors tdf8599a i 2 c-bus controlled dual channel class-d power amplifier 8.6.2.3 ac load detection ac load detection is only available in i 2 c-bus mode and is controlled using bit ib3[d4]. the default setting for bit ib3[d4] = 0 disables ac load detection. when ac load detection is enabled (bit ib3[d4] = 1), the amplifier load current is measured and compared with a reference level. pin clip is activated when this threshold is reached. using this information, ac load detection can be performed using a predetermined input signal frequency and level. the frequency and signal level should be chosen so that the load current exceeds the programmed current threshold when the ac coupled load (tweeter) is present. 8.6.2.4 clip detection clip detection gives info rmation for clip levels ? 0.2 %. pin clip is used as the output for the clip detection circuitry on both channel 1 and channel 2. setting either bit ib1[d5] or bit ib2[d5] to logic 0 defines which channel reports clip information on the clip pin. fig 19. recommended start-up sequence with dc load detection enabled 001aaj061 no no yes yes restart dc load start amplifier anyway i 2 c-bus tx ib1[d0] = 1 startup ib2[d2] = 1 enable dc load ib1[d1] = 1 disable channel 1 ib2[d1] = 1 disable channel 2 i 2 c-bus rx db1[d4] = 1 channel 1 open load db2[d4] = 1 channel 2 open load db1[d6] = 1 dc load valid i 2 c-bus tx ib1[d0] = 1 startup ib2[d2] = 0 disable dc load ib1[d1] = 0 enable channel 1 ib2[d1] = 0 enable channel 2 i 2 c-bus tx ib1[d0] = 1 startup ib2[d2] = 0 disable dc load ib1[d1] = 1 disable channel 1 ib2[d1] = 1 disable channel 2 i 2 c-bus tx ib1[d0] = 1 startup ib2[d2] = 1 enable dc load ib1[d1] = 1 disable channel 1 ib2[d1] = 1 disable channel 2 error handling count = 0 wait dc load count = count + 1 db1[d6] = 1 dc load valid count countmax
tdf8599a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 2 may 2013 22 of 55 nxp semiconductors tdf8599a i 2 c-bus controlled dual channel class-d power amplifier 8.6.3 start-up and shutdown sequence to prevent switch on or switch off ?pop noises?, a capacitor (c svrr ) connected to pin svrr is used to smooth start-up and shutdown. during start-up and shutdown, the output voltage tracks the voltage on pin svrr. increasing c svrr results in a longer start-up and shutdown time. enhanced pop noise performance is achieved by muting the amplifier until the svrr voltage reaches its final value and the outputs start switching. the capacitor value on pin sel_mute (c on ) determines the unmute and mute timing. the voltage on pin sel_mute determines the amplifier gain. increasing c on increases the unmute and mute times. in addition, a larger c on value increases the dc load detection cycle. when the amplifier is switched off with an i 2 c-bus command or by pulling pin en low, the amplifier is first muted and then capacitor (c svrr ) is discharged. in slave mode, the device enters the off state immediately after capacitor (c svrr ) is discharged. in master mode, the clock is kept active by an additional delay (t d (2) ) of approximately 50 ms to allow slave devices to enter the off state. when an external clock is connected to pi n oscio (in slave mode), the clock must remain active during the shutdown sequence for delay (t d (1) ) to ensure that the slaved tdf8599a devices are able to enter the off state. (1) shutdown hold delay. (2) master mode shutdown delay. (3) shutdown delay. fig 20. start-up and shutdown timing in i 2 c-bus mode with dc load detection 001aai790 v dda diag en acgnd ib1[d0] and ib2[d0] = 0 sel_mute svrr outn t d (2) t d (1) t d(mute-fgain) mute delay t d(stb-mute) t wake t det(dcload) t d (3)
tdf8599a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 2 may 2013 23 of 55 nxp semiconductors tdf8599a i 2 c-bus controlled dual channel class-d power amplifier 9. i 2 c-bus specification tdf8599a address with hardware address select. [1] required external resistor accuracy is 1 %. [2] short circuited to ground. in i 2 c-bus mode, pins mod and ads can be latched using the i 2 c-bus command ib3[d7] = 1. this avoids disturbances from amplifier outputs of other tdf8599a devices in the same application switching and gener ating incorrect information on the mod and ads pins. (1) shutdown hold delay. (2) shutdown delay. (3) master mode shutdown delay. fig 21. start-up and shutdown timing in non-i 2 c-bus mode 001aai791 v dda diag en t d (2) t d (1) t d (3) t d(stb-mute) acgnd sel_mute svrr outn t d(mute-fgain) table 13. i 2 c-bus write address selection using pins mod and ads r ads [1] (k ? ) r mod [1] (k ? ) r/w stereo mode parallel mode 0 [2] 4.7 13 33 100 open open 58h 68h 78h 58h 68h 78h 1 = read from tdf8599a 0 = write to tdf8599a 100 56h 66h 76h 56h 66h 76h 33 54h 64h 74h 54h 64h 74h 13 52h 62h 72h 52h 62h 72h 4.7 50h 60h 70h 50h 60h 70h 0 [2] non-i 2 c-bus mode select
tdf8599a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 2 may 2013 24 of 55 nxp semiconductors tdf8599a i 2 c-bus controlled dual channel class-d power amplifier in non-i 2 c mode or when ib3[d7] = 0, the information on the mod and ads pins is latched when one of the tdf8599a?s outputs starts switching. (1) when scl is high, sda changes to form the start or stop condition. (1) sda is allowed to change. (2) all data bits must be valid on the positive edges of scl. fig 22. i 2 c-bus start and stop conditions fig 23. data bits sent from master microprocessor (m? p) stop start 001aai792 scl sda mp slave (1) scl sda 001aai793 (2) (1) mp slave (1) to stop the transfer after the last acknowledge a stop condition must be generated. fig 24. i 2 c-bus write 001aai794 lsb + 1 lsb + 1 lsb msb ? 1 msb msb ? 1 msb ack ack ack (1) ack stop write data write start address 12 789 789 12 scl sda mp slave (1) to stop the transfer, the last byte must not be ack nowledged (sda is high) and a stop condition must be generated. fig 25. i 2 c-bus read 001aai795 lsb + 1 lsb + 1 lsb msb ? 1 msb msb ? 1 msb ack ack (1) acknowledge stop read data read start address 12 789 789 12 scl sda mp slave
tdf8599a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 2 may 2013 25 of 55 nxp semiconductors tdf8599a i 2 c-bus controlled dual channel class-d power amplifier 9.1 instruction bytes if r/w bit = 0, the tdf8599a expects three instr uction bytes: ib1, ib2 and ib3. after a power-on reset, all unspe cified instruction bits must be set to zero. [1] see section 8.3.3 on page 9 for information on ib1[d4] and ib1[d3]. [2] see table 15 ? phase shift bit settings ? for information on ib3[d3] to ib3[d1]. [3] see table 4 for information on ib1[d0] and ib2[d0]. table 14. instruction byte descriptions bit value description instruction byte ib1 instruction byte ib2 instruction byte ib3 d7 0 offset detection on pin diag offset pr otection on latch information on pins ads and mod when the amplifier starts switching 1 no offset detection on pin diag offset pr otection off latch information on pins ads and mod; see section 9 on page 23 d6 0 channel 1 offset monitoring on channel 2 offset monitoring on - 1 channel 1 offset monitoring off channel 2 offset monitoring off - d5 0 channel 1 clip detect on pin clip channel 2 clip detect on pin clip - 1 channel 1 no clip detect on pin clip channel 2 no clip detect on pin clip - d4 0 disable frequency hopping thermal pre-warning on pin clip disable ac load detection 1 enable frequency hopping [1] no thermal pre warning on pin clip enable ac load detection d3 0 oscillator frequency as set with r osc ? 10 % temperature pre-warning at 140 ? c oscillator phase shift bits ib3[d3] to ib3[d1] [2] 1 oscillator frequency as set with r osc +10% temperature pre-warning at 120 ?c d2 0 - dc-load detection disabled 1 - dc-load detection enabled d1 0 channel 1 enabled channel 2 enabled 1 channel 1 disabled channel 2 disabled d0 0 tdf8599a in standby mode all channels operating ad modulation 1 tdf8599a in mute or operating modes [3] all channels muted bd modulation table 15. phase shift bit settings d3 d2 d1 phase 0000 001 1 4 ? 010 1 3 ? 011 1 2 ? 100 2 3 ? 101 3 4 ?
tdf8599a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 2 may 2013 26 of 55 nxp semiconductors tdf8599a i 2 c-bus controlled dual channel class-d power amplifier 9.2 data bytes if r/w = 1, the tdf8599a sends two data bytes to the microprocessor (db1 and db2). all short diagnostic and offset protection bits are latched. in addition, all bits are reset after a read operation except the dc load detection bits (dbx[d4], db1[d6]) . the default setting for all bits is logic 0. in parallel mode, the diagnostic information is stored in byte db1. data byte db1[d7] indicates whether the inst ruction bits have been set to logic 0. in principle, db1[d7] is set after a por or wh en all the instruction bits are programmed to logic 0. pin diag is driven high when bit db1[d7] = 1. table 16. description of data bytes bit value db1 channel 1 db2 channel 2 d7 0 at least 1 instruction bit set to logic 1 below maximum temperature 1 all instruction bits are set to lo gic 0 maximum temperature protection activated d6 0 invalid dc load data no temperature warning 1 valid dc load data temperature pre-warning active d5 0 no overvoltage no undervoltage 1 overvoltage protection active undervoltage protection active d4 0 speaker load channel 1 speaker load channel 2 1 open load channel 1 open load channel 2 d3 0 no shorted load channel 1 no shorted load channel 2 1 shorted load channel 1 shorted load channel 2 d2 0 no offset reserved 1 offset detected reserved d1 0 no short to v p channel 1 no short to v p channel 2 1 short to v p channel 1 short to v p channel 2 d0 0 no short to ground channel 1 no short to ground channel 2 1 short to ground channel 1 short to ground channel 2
tdf8599a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 2 may 2013 27 of 55 nxp semiconductors tdf8599a i 2 c-bus controlled dual channel class-d power amplifier 10. limiting values [1] floating condition assumed for outputs. [2] current limiting concept. [3] human body model (hbm). [4] charged-device model (cdm). [5] the output pins are defined as the output pins of the filter connected between the tdf8599a output pins and the load. table 17. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v p supply voltage operating mode - 40 v off state [1] ? 1+50v load dump; duration 50 ms; t r > 2.5 ms -50v i orm repetitive peak output current maximum output current limiting [2] 8- a i om peak output current maximum; non-repetitive stereo mode - 18 a parallel mode - 12 a v i input voltage pins scl, sda, ads, mod, ssm, oscio, en and sel_mute 05.5v pins in1n, in1p, in2n and in2p 010v v o output voltage pins diag and clip 0 10 v r esr equivalent series resistance as seen between pins v p and pgndn -350m ? t j junction temperature - 150 ?c t stg storage temperature ? 55 +150 ?c t amb ambient temperature ? 40 +85 ?c v esd electrostatic discharge voltage hbm [3] c = 100 pf; r s =1.5k ? - 2000 v cdm [4] non-corner pins - 500 v corner pins - 750 v v (prot) protection voltage ac and dc short circuit voltage of output pins across load and to supply and ground [5] 0v p v
tdf8599a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 2 may 2013 28 of 55 nxp semiconductors tdf8599a i 2 c-bus controlled dual channel class-d power amplifier 11. thermal characteristics 12. static characteristics table 18. thermal characteristics symbol parameter conditions typ unit r th(j-a) thermal resistance from junction to ambient in free air 35 k/w r th(j-c) thermal resistance from junction to case 1 k/w table 19. static characteristics v p =v dda = 14.4 v; f osc = 320 khz; ? 40 ? c < t amb < +85 ? c; unless otherwise specified. symbol parameter conditions min typ max unit supply v p supply voltage 8 14.4 35 v i p supply current off state; t j ? 85 ?c; v p = 14.4 v - 2 10 ? a i q(tot) total quiescent current operating mode; no load, snubbers and filter connected -90120ma series resistance output switches r dson drain-source on-state resistance power switch; t j =25 ?c- 1 7 0 1 8 0 m ? t j = 100 ?c- 2 3 5 2 5 0 m ? i 2 c-bus interface: pins scl and sda v il low-level input voltage 0 - 1.5 v v ih high-level input voltage 2.3 - 5.5 v v ol low-level output voltage pin sda; i load =5ma 0 - 0.4 v address, phase shift and modulation mode select: pins ads and mod v i input voltage pins not connected [1] 1.5 2 2.7 v i i input current pins shorted to gnd [1] 80 105 160 ? a enable and sel_mute inpu t: pins en and sel_mute v i input voltage pin en; off state 0 - 0.8 v pin en; standby mode; i 2 c-bus mode 2- 5v pin en; mute mode or operating mode; non-i 2 c-bus mode 2- 5v pin sel_mute; mute mode; voltage on pin en > 2 v 0- 0.8v pin sel_mute; operating mode; voltage on pin en > 2 v 3- 5v i i input current pin en; 2.5 v - - 5 ? a pin sel_mute; operating mode; 0.8 v --50 ? a
tdf8599a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 2 may 2013 29 of 55 nxp semiconductors tdf8599a i 2 c-bus controlled dual channel class-d power amplifier diagnostic output thd clip total harmonic distortion clip detection level -0.2-% v th(offset) threshold voltage for offset detection [2] [3] 123v v ol low-level output voltage diag or clip pins activated; i o =1ma --0.3v i l leakage current diag and clip pins; diagnostic not activated --50 ? a audio inputs; pins in1n, in1p, in2n and in2p v i input voltage - 2.45 - v svrr voltage and acgnd input bias voltage in mute and operating modes v ref reference voltage input acgnd pin 2 2.45 3 v half supply reference svrr pin 6.9 7.2 7.5 v amplifier outputs; pins out1 n, out1p, out2n and out2p v o(offset) output offset voltage btl; mute mode - - 25 mv btl; operating mode [4] [6] --70mv stabilizer output; pins vstab1 and vstab2 v o output voltage stabilizer output in mute mode and operating mode 8 1012v voltage protections v (prot) protection voltage undervoltage; amplifier is muted 6.8 7.2 8 v overvoltage; load dump protection is activated 37 38 - v v p that a por occurs at 3 3.7 4.6 v current protection i o(ocp) overcurrent protection output current current limiting concept 8 9.5 11 a temperature protection t prot protection temperature 155 - 160 ?c t act(th_fold) thermal foldback activation temperature gain = ? 1 db 140 - 150 ?c t j(av)(warn1) average junction temperature for pre-warning 1 ib2[d3] = 0; non-i 2 c-bus mode - 140 150 ?c t j(av)(warn2) average junction temperature for pre-warning 2 ib2[d3] = 1 - 120 130 ?c dc load detection levels: i 2 c-bus mode only [7] z th(load) load detection threshold impedance for normal speaker load; db1[d4] = 0; db2[d4] = 0 --25 ? z th(open) open load detection threshold impedance db1[d4] = 1; db2[d4] = 1 350 - - ? ac load detection levels: i 2 c-bus mode only i th(o)det(load)ac ac load detection output threshold current 250 500 700 ma table 19. static characteristics ?continued v p =v dda = 14.4 v; f osc = 320 khz; ? 40 ? c < t amb < +85 ? c; unless otherwise specified. symbol parameter conditions min typ max unit
tdf8599a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 2 may 2013 30 of 55 nxp semiconductors tdf8599a i 2 c-bus controlled dual channel class-d power amplifier [1] required resistor accuracy fo r pins ads and mod is 1 %; see section 9 on page 23 . [2] maximum leakage current from dcp pin to ground = 3 ? a. [3] the output offset values can be either positive or negative. the v th(offset) limit values (excluding typ) are the valid absolute values. [4] dc output offset voltage is applied to the output gradually during the transition between mute mode and operating mode. [5] i 2 c-bus mode only. [6] the transition time between mute mode and operating mode is determined by the time constant on the sel_mute pin. [7] the dc load valid bit db1[d6] must be used; section 8.6.2.1 on page 18 . the dc load enable bit ib2[d2] must be reset after each load detection cycle to prevent amplifier hang-up incidents. start-up/shut-dow n/mute timing t wake wake-up time on pin en before first i 2 c-bus transmission is recognized [5] --500 ? s t det(dcload) dc load detection time c on =470nf [5] -380-ms t d(stb-mute) delay time from standby to mute measured from amplifier enabling to start of unmute (no dc load detection); c svrr =47 ? f c on =470nf -140-ms t d(mute-fgain) mute to full gain delay time c on =470nf [6] -15-ms t d delay time shutdown delay time from en pin low to svrr low; voltage on pin svrr < 0.1 v; c svrr =47 ? f 200 350 550 ms shutdown delay time from en pin low to svrr low; voltage on pin svrr < 0.1 v; c svrr =47 ? f; v p =35v 300 400 700 ms shutdown hold delay time from pin en low to acgnd low; voltage on pin acgnd < 0.1 v; master mode -370-ms hold delay in master mode to allow slaved devices to shutdown f osc = 320 khz -50-ms speaker load impedance r l load resistance at supply voltage equal to or below 25 v stereo mode 1.6 4 - ? parallel mode 0.8 - - ? at supply voltage equal to or below 35 v stereo mode 3.2 4 - ? parallel mode 1.6 - - ? table 19. static characteristics ?continued v p =v dda = 14.4 v; f osc = 320 khz; ? 40 ? c < t amb < +85 ? c; unless otherwise specified. symbol parameter conditions min typ max unit
tdf8599a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 2 may 2013 31 of 55 nxp semiconductors tdf8599a i 2 c-bus controlled dual channel class-d power amplifier 12.1 switching characteristics table 20. switching characteristics v p =v dda = 14.4 v; ? 40 ? c < t amb < +85 ? c; unless otherwise specified. symbol parameter conditions min typ max unit internal oscillator f osc oscillator frequency external clock frequency; r osc =39k ? -320 -khz internal fixed frequency and spread spectrum mode frequency based on the resistor value connected to pin oscset for the master setting 300 - 450 khz master/slave setting (oscio pin) r osc oscillator resistance resistor value on pin oscset; master setting 26 39 49 k ? v ol low-level output voltage output - - 0.8 v v oh high-level output voltage output 4 - - v v il low-level input voltage input - - 0.8 v v ih high-level input voltage input 4 - - v f track tracking frequency pll enabled 300 - 500 khz n slave number of slaves driven by one master 12 - - spread spectrum mode setting ? f osc oscillator frequency variation between maximum and minimum values; spread spectrum mode activated -10 -% f sw switching frequency spread s pectrum mode activated; c ssm =1 ? f -7 -hz frequency hopping f osc(int) internal oscillator frequency change positive; ib1[d4] = 1; ib1[d3] = 1 -f osc +10% - khz change negative; ib1[d4] = 1; ib1[d3] = 0 -f osc ? 10 % - khz timing t r rise time pwm output; i o =0a - 10 - ns t f fall time pwm output; i o =0a - 10 - ns t w(min) minimum pulse width i o =0a - 80 - ns
tdf8599a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 2 may 2013 32 of 55 nxp semiconductors tdf8599a i 2 c-bus controlled dual channel class-d power amplifier 13. dynamic characteristics [1] r s(l) is the sum of the inductor series resistance from the low-pass lc filter in the application together with all resistance from pcb traces or wiring between the output pin of the tdf8599a and the inductor to the measurement poin t. lc filter dimensioning is l=10 ? h, c = 1 ? f for 4 ? load and l = 5 ? h, c = 2.2 ? f for 2 ? load. [2] output power is measured indirectly based on r dson measurement. table 21. dynamic characteristics v p =v dda = 14.4 v; r l =4 ? ; f i = 1 khz; f osc = 320 khz; r s(l) < 0.04 ? [1] ; ? 40 ? c < t amb < +85 ? c; stereo mode; unless otherwise specified. symbol parameter conditions min typ max unit p o output power stereo mode: [2] v p =14.4v; thd=1%; r l =4 ? 18 20 - w v p = 14.4 v; thd = 10 %; r l =4 ? 23 25 - w square wave (eiaj); r l =4 ? -40-w v p = 35 v; thd = 10 %; r l =4 ? -135-w v p =14.4v; thd=1%; r l =2 ? 26 29 - w v p = 14.4 v; thd = 10 %; r l =2 ? 34 38 - w square wave (eiaj); r l =2 ? -60-w parallel mode: [2] v p = 14.4 v; thd = 10 %; r l =2 ? -50-w v p = 35 v; thd = 10 %; r l =2 ? -250-w v p =25v; thd=1%; r l =1 ? 135 150 - w thd total harmonic distortion f i = 1 khz; p o =1 w [3] - 0.02 0.1 % f i =10khz; p o =1 w [3] - 0.02 0.1 % g v(cl) closed-loop voltage gain 25 26 27 db ? cs channel separation f i = 1 khz; p o =1 w - 70 - db svrr supply voltage rejection ratio operating mode f ripple =100hz [4] 60 70 - db f ripple = 1 khz [4] 60 70 - db mute mode f ripple = 1 khz [4] 60 70 - db off state and standby mode f ripple = 1 khz [4] -90-db ?z i(dif) ? differential input impedance 60 100 150 k ? v n(o) output noise voltage operating mode bd mode [5] -6077 ? v ad mode [5] -100140 ? v mute mode bd mode [6] -2532 ? v ad mode [6] -85110 ? v ? bal(ch) channel balance - 0 1 db ? mute mute attenuation [7] 66 - - db cmrr common mode rejection ratio v i(cm) =1 v rms 65 80 - db ? po output power efficiency p o =20 w - 90 - %
tdf8599a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 2 may 2013 33 of 55 nxp semiconductors tdf8599a i 2 c-bus controlled dual channel class-d power amplifier [3] total harmonic distortion is measured at the bandwidth of 22 hz to 20 khz, aes brick wall. t he maximum limit is guaranteed but may not be 100 % tested. [4] v ripple =v ripple(max) = 2 v (p-p); r s =0 ? . [5] b = 22 hz to 20 khz, aes brick wall, r s =0 ? . [6] b = 22 hz to 20 khz, aes brick wall, independent of r s . [7] v i =v i(max) = 0.5 v rms. 14. application information 14.1 output power estimation (stereo mode) the output power, just before clipping, can be estimated using equation 5 : (5) where, ? v p = supply voltage (v) ? r l = load impedance ( ? ) ? r dson = drain source on-s tate resistance ( ? ) ? r s = series resistance of the output inductor ( ? ) ? t w(min) = minimum pulse width(s) depending on output current (s) ? f osc = oscillator frequency in hz (typically 320 khz) the output power at 10 % thd can be estimated by: where p o(1) = 0.5 % and p o(2) =10%. figure 26 and figure 27 show the estimated output power at thd = 0.5 % and thd = 10 % as a function of supply voltage for different load impedances in stereo mode. p o r l r l 2r dson r s + ?? ? + ----------------------------------------------------- ?? ?? 1t wmin ?? f osc 2 -------- ? ? ?? ?? v p ? ? ? 2 ? ? ? 2r l ? ------------------------------------------------------------------------------------------------------------------------------------- w ?? = p o2 ?? 1.25 p o1 ?? ? =
tdf8599a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 2 may 2013 34 of 55 nxp semiconductors tdf8599a i 2 c-bus controlled dual channel class-d power amplifier 14.2 output power estimat ion (parallel mode) figure 28 and figure 29 show the estimated output power at thd = 0.5 % and thd = 10 % as a function of the supply voltage for different load impedances in parallel mode. thd = 0.5 %. r dson =0.2 ? (at t j = 100 ? c), r s =0.05 ? , t w(min) = 190 ns and i o(ocp) = 8 a (minimum). (1) r l =2 ? . (2) r l =4 ? . thd = 10 %. r dson =0.2 ? (at t j = 100 ? c), r s =0.05 ? , t w(min) = 190 ns and i o(ocp) = 8 a (minimum). (1) r l =2 ? . (2) r l =4 ? . fig 26. p o as a function of v p in stereo mode with thd = 0.5 % fig 27. p o as a function of v p in stereo mode with thd = 10 % v p (v) 840 32 24 16 (1) (2) 001aaj181 60 40 100 140 20 80 120 p o (w) 0 v p (v) 840 32 24 16 (1) (2) 001aaj182 80 40 120 160 p o (w) 0
tdf8599a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 2 may 2013 35 of 55 nxp semiconductors tdf8599a i 2 c-bus controlled dual channel class-d power amplifier 14.3 output current limiting the peak output current is inte rnally limited to 8 a maximum. during normal operation, the output current should not exceed this threshold level otherwise the outp ut signal will be distorted. the peak output cu rrent can be estimated using equation 6 : (6) ? i o = output current (a) ? v p = supply voltage (v) ? r l = load impedance ( ? ) ? r dson = on-resistance of power switch ( ? ) ? r s = series resistance of output inductor ( ? ) example: a 2 ? speaker can be used with a supply voltage of 19 v before current limiting is triggered. current limiting (clipping) avoids audio holes but can cause distortion similar to voltage clipping. in parallel mode, the output cu rrent is internally limited above 16 a. thd = 0.5 %. r dson =0.1 ? (at t j = 100 ? c), r s = 0.025 ? , t w(min) = 190 ns and i o(ocp) = 16 a (minimum). (1) r l =1 ? . (2) r l =2 ? . (3) r l =4 ? . thd = 10 %. r dson =0.1 ? (at t j = 100 ? c), r s = 0.025 ? , t w(min) = 190 ns and i o(ocp) = 16 a (minimum). (1) r l =1 ? . (2) r l =2 ? . (3) r l =4 ? . fig 28. p o as a function of v p in parallel mode with thd = 0.5 % fig 29. p o as a function of v p parallel mode with thd = 10 % v p (v) 840 32 24 16 (1) (2) (3) 001aaj183 150 50 100 200 250 p o (w) 0 v p (v) 840 32 24 16 (1) (2) (3) 001aaj184 100 200 300 50 150 250 p o (w) 0 i o v p r l 2 + r dson r s + ?? ? ----------------------------------------------------- 8 [a] ??
tdf8599a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 2 may 2013 36 of 55 nxp semiconductors tdf8599a i 2 c-bus controlled dual channel class-d power amplifier 14.4 speaker configuration and impedance a flat-frequency response (due to a 2 nd order butterworth filter) is obtained by changing the low-pass filter components (l lc , c lc ) based on the speaker configuration and impedance. ta b l e 2 2 shows the required values. remark: when using a 1 ? load impedance in parallel mode, the outputs are shorted after the low-pass filter switches two 2 ? filters in parallel. 14.5 heat sink requirements in most applications, it is necessary to conne ct an external heat sink to the tdf8599a. thermal foldback activates at t j =140 ? c. the expression below shows the relationship between the maximum power dissipation before activation of thermal foldback and the total thermal resistance from junction to ambient: (7) p max is determined by the efficiency ( ? ) of the tdf8599a. the efficiency measured as a function of output power is given in figure 43 . the power dissipation can be derived as a function of output power (see figure 42 ). example 1: ? v p =14.4v ? p o =2 ? 25 w into 4 ? (thd = 10 % continuous) ? t j(max) = 140 ? c ? t amb = 25 ? c ? p max = 5.8 w (from figure 42 ) ? the required r th(j-a) =115 ? c / 5.8w=19k/w the total thermal resistance r th(j-a) consists of: r th(j-c) + r th(c-h) + r th(h-a) where: ? thermal resistance from junction to case (r th(j-c) ) = 1 k/w ? thermal resistance from case to heat sink (r th(c-h) ) = 0.5 k/w to 1 k/w (depending on mounting) ? thermal resistance from heat sink to ambient (r th(h-a) ) would then be 19 ? (1 + 1) = 17 k/w. if an audio signal has a crest factor of 10 (the ratio between peak power and average power = 10 db) then t j will be much lower. table 22. filter component values load impedance ( ? ) l lc ( ? h) c lc ( ? f) 12.54.4 252.2 4101 r th j-a ?? t jmax ?? t amb ? p max ---------------------------------- - k/w ?? =
tdf8599a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 2 may 2013 37 of 55 nxp semiconductors tdf8599a i 2 c-bus controlled dual channel class-d power amplifier example 2: ? v p =14.4v ? p o =2 ? (25 w / 10) = 2 ? 2.5 w into 4 ? (audio with crest factor of 10) ? t amb = 25 ? c ? p max =2.5w ? r th(j-a) =19k/w ? t j(max) = 25 ? c + (2.5 w ? 19 k/w) = 72 ? c 14.6 curves measured in reference design (1) v p = 14.4 v; r l =2 ? at 100 hz. (2) v p = 14.4 v; r l =2 ? at 1 khz. (3) v p = 14.4 v, r l =2 ? at 6 khz. (1) v p = 14.4 v; r l =4 ? at 100 hz. (2) v p = 14.4 v; r l =4 ? at 1 khz. (3) v p = 14.4 v, r l =4 ? at 6 khz. fig 30. thd + n as a function of output power with a 2 ? load; v p = 14.4 v fig 31. thd + n as a function of output power with a 4 ? load; v p = 14.4 v 001aaj185 p o (w) 10 ?1 10 2 10 1 10 ?1 10 ?2 10 1 10 2 thd + n (%) 10 ?3 (1) (2) (3) 001aaj186 p o (w) 10 ?1 10 2 10 1 10 ?1 10 ?2 10 1 10 2 thd + n (%) 10 ?3 (1) (2) (3)
tdf8599a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 2 may 2013 38 of 55 nxp semiconductors tdf8599a i 2 c-bus controlled dual channel class-d power amplifier (1) v p =35v; r l =2 ? at 100 hz. (2) v p =35v; r l =2 ? at 1 khz. (3) v p =35v, r l =2 ? at 6 khz. (1) v p =35v; r l =4 ? at 100 hz. (2) v p =35v; r l =4 ? at 1 khz. (3) v p =35v, r l =4 ? at 6 khz. fig 32. thd + n as a function of output power with a 2 ? load; v p = 35 v fig 33. thd + n as a function of output power with a 4 ? load; v p = 35 v (1) v p = 14.4 v; r l =2 ? at 1 w. (2) v p = 14.4 v; r l =2 ? at 10 w. (1) v p = 14.4 v; r l =4 ? at 1 w. (2) v p = 14.4 v; r l =4 ? at 10 w. fig 34. thd + n as a function of frequency with a 2 ? load, bd modulation; v p = 14.4 v fig 35. thd + n as a function of frequency with a 4 ? load, bd modulation; v p = 14.4 v 001aaj187 10 ?1 10 ?2 10 1 10 2 thd + n (%) 10 ?3 p o (w) 10 ?1 10 3 10 2 110 (1) (2) (3) 001aaj188 10 ?1 10 ?2 10 1 10 2 thd + n (%) 10 ?3 p o (w) 10 ?1 10 3 10 2 110 (1) (2) (3) 001aaj190 10 ?1 10 ?2 1 thd + n (%) 10 ?3 f (hz) 10 10 5 10 4 10 2 10 3 (1) (2) 001aaj189 10 ?1 10 ?2 1 thd + n (%) 10 ?3 f (hz) 10 10 5 10 4 10 2 10 3 (1) (2)
tdf8599a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 2 may 2013 39 of 55 nxp semiconductors tdf8599a i 2 c-bus controlled dual channel class-d power amplifier (1) v p =35v; r l =2 ? at 1 w. (2) v p =35v; r l =2 ? at 10 w. fig 36. thd + n as a function of frequency with a 2 ? load, bd modulation; v p = 35 v fig 37. gain as a function of frequency 001aaj191 10 ?1 10 ?2 1 thd + n (%) 10 ?3 f (hz) 10 10 5 10 4 10 2 10 3 (1) (2) 001aaj192 24 26 22 28 30 g (db) 20 f (hz) 10 10 5 10 4 10 2 10 3 f=1khz; r l =2 ? . (1) thd = 1 %. (2) thd = 10 %. (3) maximum output power. f=1khz; r l =4 ? . (1) thd = 1 %. (2) thd = 10 %. (3) maximum output power. fig 38. output power as a function of supply voltage with a 2 ? load fig 39. output power as a function of supply voltage with a 4 ? load v p (v) 10 30 26 18 22 14 001aaj193 80 40 120 160 p o (w) 0 (3) (2) (1) v p (v) 10 35 30 20 25 15 001aaj194 80 160 240 40 120 200 p o (w) 0 (2) (1) (3)
tdf8599a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 2 may 2013 40 of 55 nxp semiconductors tdf8599a i 2 c-bus controlled dual channel class-d power amplifier v p = 14.4 v; r i =4 ? ;p o =1w. (1) channel 1 to channel 2. (2) channel 2 to channel 1. v p = 14.4 v; r i =4 ? ;p o =10w. (1) channel 1 to channel 2. (2) channel 2 to channel 1. fig 40. channel separation as a function of frequency with 1 w output power fig 41. channel separation as a function of frequency with 10 w output power 001aaj195 ?80 ?90 ?70 ?60 cs (db) ?100 f (hz) 10 10 5 10 4 10 2 10 3 (2) (1) 001aaj196 ?80 ?90 ?70 ?60 cs (db) ?100 f (hz) 10 10 5 10 4 10 2 10 3 (2) (1) (1) v p = 14.4 v; r l =2 ? at 1 khz. (2) v p = 14.4 v; r l =4 ? at 1 khz. (1) v p = 14.4 v; r l =2 ? at 1 khz. (2) v p = 14.4 v; r l =4 ? at 1 khz. fig 42. power dissipation as a function of output power fig 43. efficiency as a function of total output power p o (w) 050 40 20 30 10 001aaj197 10 20 30 p d (w) 0 (1) (2) p o (w) 050 40 20 30 10 001aaj198 40 60 20 80 100 (%) 0 (1) (2)
tdf8599a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 2 may 2013 41 of 55 nxp semiconductors tdf8599a i 2 c-bus controlled dual channel class-d power amplifier v p =35v; r l =4 ? .v p =35v; r l =4 ? . fig 44. power dissipation as a function of total output power with both channels driven fig 45. efficiency as a function of output power of one channel with both channels driven p o (w) 0 150 120 60 90 30 001aaj199 20 10 30 40 p d (w) 0 p o (w) 0 150 120 60 90 30 001aaj200 40 60 20 80 100 (%) 0 v p = 14.4 v; v i =1vrms. fig 46. cmrr as a function of frequency 001aak079 ?82 ?78 ?86 ?74 ?70 cmrr (db) ?90 f (hz) 10 10 5 10 4 10 2 10 3
tdf8599a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 2 may 2013 42 of 55 nxp semiconductors tdf8599a i 2 c-bus controlled dual channel class-d power amplifier 14.7 typical appli cation schematics dual btl mode (stereo) in non-i 2 c-bus mode with dc offset protec tion disabled, spread spectrum mode enabled bd modulation. (1) see figure 3 on page 6 for a diagram of the connection for pins en and sel_mute. (2) see section 8.3.2 on page 8 for detailed information. (3) see section 8.5.5 on page 16 for detailed information on dc offset protection. fig 47. example application diagram: dual btl in non-i 2 c-bus mode 001aak080 22 39 k 10 k 10 k 4.7 k 10 10 22 100 f 35 v 100 f 35 v 100 nf 15 nf 470 nf 100 nf 15 nf 470 pf 470 pf 470 pf 470 pf c lc c in1p 470 nf c in1n 470 nf c in2p 470 nf 470 nf 2.2 f 47 f c in2n l lc l lc c lc 100 nf pgnd1 pgnd1 v p1 v p1 v p1 v p2 v pa tdf8599a bead bead bead bead out1n out1p out1n v p gnd out1p vstab1 gndd/hw 33 32 31 30 29 28 34 35 36 25 24 23 22 21 20 19 26 27 4 5 6 7 8 9 3 2 1 12 13 14 15 16 17 18 11 10 boot1n boot1p v p1 pgnd1 pgnd1 pgnd2 v ddd 1000 f 35 v 100 nf 220 nf vstab2 dcp oscio 220 nf 22 10 10 22 100 nf 15 nf 100 nf 15 nf 470 pf 470 pf 470 pf 470 pf c lc l lc l lc c lc 100 nf pgnd2 v p2 v p2 pgnd2 out2p out2n out2p out2n boot2p boot2n v p2 pgnd2 in2n agnd in2p in1p acgnd svrr en sel_mute in1n in2n 100 nf 100 nf 1 f (2) c acgnd enable (1) mute/on (1) in2p in1p in1n scl ssm oscset v dda sda v pull-up v pull-up v pa bd modulation setting master mode non-i 2 c-bus mode ads diag mod clip (3)
tdf8599a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 2 may 2013 43 of 55 nxp semiconductors tdf8599a i 2 c-bus controlled dual channel class-d power amplifier dual btl mode (stereo) in i 2 c-bus mode with dc offset protection enabled, spread spectrum mode disabled. (1) see figure 3 on page 6 for a diagram of the connection for pins en and sel_mute. (2) see section 8.3.2 on page 8 for detailed information. (3) see section 8.5.5 on page 16 for detailed information on dc offset protection. fig 48. example application diagram: dual btl in i 2 c-bus mode 001aak081 22 39 k 10 k 10 k 13 k 10 10 22 100 f 35 v 100 f 35 v 100 nf 15 nf 470 nf 100 nf 15 nf 470 pf 470 pf 470 pf 470 pf c lc c in1p 470 nf c in1n 470 nf c in2p 470 nf 470 nf 2.2 f 47 f c in2n l lc l lc c lc 100 nf pgnd1 pgnd1 v p1 v p1 v p1 v p2 v pa tdf8599a bead bead r ads bead bead out1n out1p out1n v p gnd out1p vstab1 gndd/hw 33 32 31 30 29 28 34 35 36 25 24 23 22 21 20 19 26 27 4 5 6 7 8 9 3 2 1 12 13 14 15 16 17 18 11 10 boot1n boot1p v p1 pgnd1 pgnd1 pgnd2 v ddd 1000 f 35 v 4.7 f 100 nf 220 nf vstab2 dcp oscio 220 nf 22 10 10 22 100 nf 15 nf 100 nf 15 nf 470 pf 470 pf 470 pf 470 pf c lc l lc l lc c lc 100 nf pgnd2 pgnd2 v p2 v p2 out2p out2n out2p out2n boot2p boot2n v p2 pgnd2 in2n agnd in2p in1p acgnd svrr en sel_mute (1) in1n in2n 100 nf 100 nf (2) c acgnd enable (1) in2p in1p in1n scl ssm oscset v dda sda v pull-up v pull-up v pa stereo mode setting connect to p master mode i 2 c-bus address select ads diag mod clip (3)
tdf8599a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 2 may 2013 44 of 55 nxp semiconductors tdf8599a i 2 c-bus controlled dual channel class-d power amplifier single btl mode (parallel) in i 2 c-bus mode with dc offset protection enabled, spread spectrum mode disabled. (1) see figure 3 on page 6 for a diagram of the connection for pins en and sel_mute. (2) see section 8.3.2 on page 8 for detailed information. (3) see section 8.5.5 on page 16 for detailed information on dc offset protection. fig 49. example application diagram: single btl in i 2 c-bus mode 001aak082 22 39 k 10 k 10 k 33 k 10 10 22 100 f 35 v 100 f 35 v 100 nf 15 nf 470 nf 100 nf 15 nf 470 pf 470 pf 470 pf 470 pf c lc c inp 470 nf c inn 470 nf 2.2 f 47 f l lc l lc c lc 100 nf pgnd1 pgnd1 v p1 v p1 v p1 v p2 v pa tdf8599a bead bead r ads bead bead out1n out1p outn v p gnd outp vstab1 gndd/hw 33 32 31 30 29 28 34 35 36 25 24 23 22 21 20 19 26 27 4 5 6 7 8 9 3 2 1 12 13 14 15 16 17 18 11 10 boot1n boot1p v p1 pgnd1 pgnd1 pgnd2 v ddd 1000 f 35 v 4.7 f 100 nf 220 nf vstab2 dcp oscio 220 nf 10 10 15 nf 100 nf 15 nf 470 pf 470 pf 470 pf 470 pf l lc l lc pgnd2 pgnd2 v p2 v p2 out2p out2n boot2p boot2n v p2 pgnd2 in2n agnd in2p in1p acgnd svrr en sel_mute (1) in1n 100 nf 100 nf c acgnd enable (1) inp inn scl ssm oscset v dda sda v pull-up v pull-up v pa parallel mode setting connect to p fixed frequency (2) master mode i 2 c-bus address select ads diag mod clip (3)
tdf8599a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 2 may 2013 45 of 55 nxp semiconductors tdf8599a i 2 c-bus controlled dual channel class-d power amplifier i 2 c-bus mode: dual btl in master mode, one btl in slave mode; dc offset protection enabled. (1) see figure 3 on page 6 for a diagram of the connection for pins en and sel_mute. (2) see section 8.3.2 on page 8 for detailed information. (3) see section 8.5.5 on page 16 for detailed information on disabling dc offset protection. (4) see section 8.3.4 on page 10 for detailed information on pll operation. fig 50. example application diagram: dual btl master, single btl slave in i 2 c-bus mode 22 39 k 20 k 10 k 10 k 13 k 10 10 22 100 f 35 v 100 f 35 v 100 nf 15 nf 470 nf 100 nf 15 nf 470 pf 470 pf 470 pf 470 pf c lc c in1p 470 nf c in1n 470 nf c in2p 470 nf 470 nf 2.2 f 47 f 1 f c in2n l lc l lc c lc 100 nf pgnd1 pgnd1 v p1 v p1 v p1 v p2 v pa tdf8599a bead bead r ads bead bead out1n out1p out1n v p gnd out1p vstab1 gndd/hw 33 32 31 30 29 28 34 35 36 25 24 23 22 21 20 19 26 27 4 5 6 7 8 9 3 2 1 12 13 14 15 16 17 18 11 10 boot1n boot1p v p1 pgnd1 pgnd1 pgnd2 v ddd 1000 f 35 v 4.7 f 100 nf 220 nf vstab2 dcp oscio 220 nf 22 10 10 22 100 nf 15 nf 100 nf 15 nf 470 pf 470 pf 470 pf 470 pf c lc l lc l lc c lc 100 nf pgnd2 pgnd2 v p2 v p2 out2p master slave out2n out2p out2n boot2p boot2n v p2 pgnd2 in2n agnd in2p in1p acgnd svrr en (1) sel_mute (1) in1n in2n 100 nf 100 nf c acgnd enable in2p in1p in1n scl ssm oscset v dda sda v papull-up v pull-up v pa stereo mode setting spread spectrum mode (2) dc offset protection enabled (3) dc offset protection enabled (3) master mode i 2 c-bus address select ads diag mod clip 001aak083 22 5.1 k 10 k 10 k 33 k 10 10 22 100 nf 15 nf 470 nf 100 nf 15 nf 470 pf 470 pf 470 pf 470 pf c lc c inp 470 nf c inn 470 nf 2.2 f 47 f l lc l lc c lc 100 nf pgnd1 pgnd1 v p1 v p1 tdf8599a bead r ads out1n out1p out3n out3p vstab1 gndd/hw 33 32 31 30 29 28 34 35 36 25 24 23 22 21 20 19 26 27 4 5 6 7 8 9 3 2 1 12 13 14 15 16 17 18 11 10 boot1n boot1p v p1 pgnd1 v ddd 4.7 f 100 nf 220 nf vstab2 dcp oscio 220 nf 10 10 15 nf 100 nf 15 nf 470 pf 470 pf 470 pf 470 pf l lc l lc pgnd2 pgnd2 v p2 v p2 out2p out2n boot2p boot2n v p2 pgnd2 in2n agnd in2p in1p acgnd svrr en (1) sel_mute (1) in1n 100 nf 10 nf 270 nf c acgnd in3p in3n scl ssm oscset v dda sda v pull-up v pull-up v pa parallel mode setting connect to p phase lock operation (4) slave mode i 2 c-bus address select ads diag mod clip
tdf8599a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 2 may 2013 46 of 55 nxp semiconductors tdf8599a i 2 c-bus controlled dual channel class-d power amplifier 15. package outline fig 51. package outline sot851-2 (hsop36) references outline version european projection issue date iec jedec jeita sot851-2 sot851-2 04-05-04 hsop36: plastic, heatsink small outline package; 36 leads; low stand-off height b p z 118 36 19 d 1 d 2 e 1 e a h e d e 2 y x e w m pin 1 index va m x l p detail x (a 3 ) a 2 a 4 c a q 0 5 10 mm scale unit a 4 (1) mm + 0.08 ? 0.04 3.5 0.35 dimensions (mm are the original dimensions) notes 1. limits per individual lead. 2. plastic or metal protrusions of 0.25 mm maximum per side are not included. a max. a 2 3.5 3.2 d 2 1.1 0.9 h e 14.5 13.9 l p 1.1 0.8 q 1.7 1.5 2.55 2.20 v 0.25 w 0.12 yz 8 0 0.07 x 0.03 d 1 13.0 12.6 e 1 6.2 5.8 e 2 2.9 2.5 b p c 0.32 0.23 e 0.65 d (2) 16.0 15.8 e (2) 11.1 10.9 0.38 0.25 a 3
tdf8599a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 2 may 2013 47 of 55 nxp semiconductors tdf8599a i 2 c-bus controlled dual channel class-d power amplifier 16. handling information in accordance with snw-fq-611-d. the number of the quality specification can be found in the quality reference handbook. the handbook can be ordered using the code 9398 510 63011. 17. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 ?surface mount reflow soldering description? . 17.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electr ical circuits. the soldered joint provides both the mechanical and the electrical connection. th ere is no single sold ering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for fine pitch smds. reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 17.2 wave and reflow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased pr obability of bridging. the reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. leaded packages, packages with solder balls, and leadless packages are all reflow solderable. key characteristics in both wave and reflow soldering are: ? board specifications, in cluding the board finish , solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivit y level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering 17.3 wave soldering key characteristics in wave soldering are:
tdf8599a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 2 may 2013 48 of 55 nxp semiconductors tdf8599a i 2 c-bus controlled dual channel class-d power amplifier ? process issues, such as application of adhe sive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath specifications, including temperature and impurities 17.4 reflow soldering key characteristics in reflow soldering are: ? lead-free versus snpb solderi ng; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see figure 52 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? reflow temperature profile; this profile includ es preheat, reflow (in which the board is heated to the peak temperature) and cooling down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classified in accordance with ta b l e 2 3 and 24 moisture sensitivity precautions, as indicat ed on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during reflow soldering, see figure 52 . table 23. snpb eutectic process (from j-std-020d) package thickness (mm) package reflow temperature ( ?c) volume (mm 3 ) < 350 ? 350 < 2.5 235 220 ? 2.5 220 220 table 24. lead-free process (from j-std-020d) package thickness (mm) package reflow temperature ( ?c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245
tdf8599a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 2 may 2013 49 of 55 nxp semiconductors tdf8599a i 2 c-bus controlled dual channel class-d power amplifier for further information on temperature profiles, refer to application note an10365 ?surface mount reflow soldering description? . 18. abbreviations msl: moisture sensitivity level fig 52. temperature profiles for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature table 25. abbreviations abbreviation description bcdmos bipolar complementary and double diffused metal-oxide semiconductor btl bridge-tied load dcp dc offset protection dmost double diffused metal-oxide semiconductor transistor emi electromagnet ic interference i 2 c inter-integrated circuit lsb least significant bit m? p master microprocessor msb most significant bit ndmost n-type double diffused metal-oxide semiconductor transistor ocp overcurrent protection otp overtemperature protection ovp overvoltage protection pll phase-locked loop por power-on reset pwm pulse-width modulation soi silicon on insulator
tdf8599a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 2 may 2013 50 of 55 nxp semiconductors tdf8599a i 2 c-bus controlled dual channel class-d power amplifier 19. revision history tfp thermal foldback protection uvp undervoltage protection wp window protection table 25. abbreviations ?continued abbreviation description table 26. revision history document id release date data sheet status change notice supersedes tdf8599a v.3 20130502 product data sheet - tdf8599a v.2 modifications: ? changed title figure 45 . tdf8599a v.2 20090630 product data sheet - tdf8599a v.1 modifications: ? data sheet status changed from objective data sheet to product data sheet. ? various minor textual inconsistencies in the data sheet corrected. ? changed section 8.2: figure 3 on page 6. ? changed section 8.2: table 4 on page 7. ? changed section 8.2: table 5 on page 7. ? changed section 8.6.3: figure 20 on page 22. ? changed section 8.6.3: figure 21 on page 23. ? changed section 14.7: figure 47 on page 42, figure 48 on page 43, figure 49 on page 44 and figure 50 on page 45. tdf8599a v.1 20090602 objective data sheet - -
tdf8599a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 2 may 2013 51 of 55 nxp semiconductors tdf8599a i 2 c-bus controlled dual channel class-d power amplifier 20. legal information 20.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 20.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 20.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such info rmation. nxp semiconductors takes no responsibility for the content in this document if provided by an information source outside of nxp semiconductors. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use in automotive applications ? this nxp semiconductors product has been qualified for use in automotive applications. unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors and its suppliers accept no liability for inclusion and/or use of nxp semiconducto rs products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification.
tdf8599a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 2 may 2013 52 of 55 nxp semiconductors tdf8599a i 2 c-bus controlled dual channel class-d power amplifier no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any licens e under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from competent authorities. quick reference data ? the quick reference data is an extract of the product data given in the limiting values and characteristics sections of this document, and as such is not comple te, exhaustive or legally binding. translations ? a non-english (translated) version of a document is for reference only. the english version shall prevail in case of any discrepancy between the translated and english versions. 20.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. i 2 c-bus ? logo is a trademark of nxp b.v. 21. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
tdf8599a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 2 may 2013 53 of 55 nxp semiconductors tdf8599a i 2 c-bus controlled dual channel class-d power amplifier 22. tables table 1. quick reference data . . . . . . . . . . . . . . . . . . . . .2 table 2. ordering information . . . . . . . . . . . . . . . . . . . . .2 table 3. pin description . . . . . . . . . . . . . . . . . . . . . . . . . .4 table 4. i 2 c-bus mode operation . . . . . . . . . . . . . . . . . . .7 table 5. non-i 2 c-bus mode operation . . . . . . . . . . . . . . .7 table 6. mode setting pin oscio . . . . . . . . . . . . . . . . . .7 table 7. oscillator modes . . . . . . . . . . . . . . . . . . . . . . .10 table 8. operation mode sele ction with the mod pin . . 11 table 9. overview of protection types . . . . . . . . . . . . . .15 table 10. overview of tdf859 9a protection circuits and amplifier states . . . . . . . . . . . . . . . . . . . . . . . . .17 table 11. available data on pins diag and clip . . . . . .18 table 12. interpretation of dc load detection bits . . . . . .20 table 13. i 2 c-bus write address selection using pins mod and ads . . . . . . . . . . . . . . . . . . . . . . . . .23 table 14. instruction byte descripti ons . . . . . . . . . . . . . .25 table 15. phase shift bit settings . . . . . . . . . . . . . . . . . . .25 table 16. description of data bytes . . . . . . . . . . . . . . . . .26 table 17. limiting values . . . . . . . . . . . . . . . . . . . . . . . . .27 table 18. thermal characteristics . . . . . . . . . . . . . . . . . .28 table 19. static characteristics . . . . . . . . . . . . . . . . . . . .28 table 20. switching characteristics . . . . . . . . . . . . . . . . .31 table 21. dynamic characteristics . . . . . . . . . . . . . . . . . .32 table 22. filter component values . . . . . . . . . . . . . . . . .36 table 23. snpb eutectic process (from j-std-020d) . . .48 table 24. lead-free process (from j-std-020d) . . . . . .48 table 25. abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .49 table 26. revision history . . . . . . . . . . . . . . . . . . . . . . . .50
tdf8599a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 2 may 2013 54 of 55 nxp semiconductors tdf8599a i 2 c-bus controlled dual channel class-d power amplifier 23. figures fig 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 fig 2. heatsink up (top view) pin configuration tdf8599ath . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 fig 3. mode selection. . . . . . . . . . . . . . . . . . . . . . . . . . . .6 fig 4. clock frequency as a function of r osc . . . . . . . . . .8 fig 5. master and slave configuration . . . . . . . . . . . . . . .8 fig 6. spread spectrum mode . . . . . . . . . . . . . . . . . . . . .9 fig 7. spread spectrum operation in master mode . . . . .9 fig 8. phase lock operation . . . . . . . . . . . . . . . . . . . . . .10 fig 9. ad/bd modulation switchin g circuit . . . . . . . . . . .12 fig 10. ad modulation . . . . . . . . . . . . . . . . . . . . . . . . . . .12 fig 11. bd modulation . . . . . . . . . . . . . . . . . . . . . . . . . . .13 fig 12. master and slave operation with 1 2 p phase shift 14 fig 13. parallel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 fig 14. dc offset protection and diagnostic output . . . . .16 fig 15. diagnostic output for short circuit conditions . . . .18 fig 16. dc load detection circuit . . . . . . . . . . . . . . . . . . .19 fig 17. dc load detection procedure . . . . . . . . . . . . . . . .19 fig 18. dc load detection limits . . . . . . . . . . . . . . . . . . . .19 fig 19. recommended start-up sequence with dc load detection enabled . . . . . . . . . . . . . . . . . . . . . . . .21 fig 20. start-up and shutdown timing in i 2 c-bus mode with dc load detection . . . . . . . . . . . . . . . . . . . . .22 fig 21. start-up and shutdown timing in non-i 2 c-bus mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 fig 22. i 2 c-bus start and stop conditions. . . . . . . . . . . . .24 fig 23. data bits sent from master microprocessor (mmp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 fig 24. i 2 c-bus write . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 fig 25. i 2 c-bus read. . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 fig 26. p o as a function of v p in stereo mode with thd = 0.5 % . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 fig 27. p o as a function of v p in stereo mode with thd = 10 % . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 fig 28. p o as a function of v p in parallel mode with thd = 0.5 % . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 fig 29. p o as a function of v p parallel mode with thd = 10 % . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 fig 30. thd + n as a function of output power with a 2 ? load; v p = 14.4 v. . . . . . . . . . . . . . . . . . . . . .37 fig 31. thd + n as a function of output power with a 4 ? load; v p = 14.4 v. . . . . . . . . . . . . . . . . . . . . .37 fig 32. thd + n as a function of output power with a 2 ? load; v p = 35 v . . . . . . . . . . . . . . . . . . . . . . .38 fig 33. thd + n as a function of output power with a 4 ? load; v p = 35 v . . . . . . . . . . . . . . . . . . . . . . .38 fig 34. thd + n as a function of frequency with a 2 ? load, bd modulation; v p = 14.4 v . . . . . . . . . . . .38 fig 35. thd + n as a function of frequency with a 4 ? load, bd modulation; v p = 14.4 v . . . . . . . . . . . .38 fig 36. thd + n as a function of frequency with a 2 ? load, bd modulation; v p = 35 v. . . . . . . . . . . . . .39 fig 37. gain as a function of frequency . . . . . . . . . . . . . .39 fig 38. output power as a function of supply voltage with a 2 ? load . . . . . . . . . . . . . . . . . . . . . . . . . . .39 fig 39. output power as a function of supply voltage with a 4 ? load . . . . . . . . . . . . . . . . . . . . . . . . . . 39 fig 40. channel separation as a function of frequency with 1 w output power. . . . . . . . . . . . . . . . . . . . . 40 fig 41. channel separation as a function of frequency with 10 w output power. . . . . . . . . . . . . . . . . . . . 40 fig 42. power dissipation as a function of output power . 40 fig 43. efficiency as a function of total output power . . . 40 fig 44. power dissipation as a function of total output power with both channels driven. . . . . . . . . . . . . 41 fig 45. efficiency as a function of output power of one channel with both channels driven . . . . . . . . . . . 41 fig 46. cmrr as a function of frequency . . . . . . . . . . . . 41 fig 47. example application diagram: dual btl in non-i 2 c-bus mode . . . . . . . . . . . . . . . . . . . . . . . . 42 fig 48. example application diagram: dual btl in i 2 c-bus mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 fig 49. example application diagram: single btl in i 2 c-bus mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 fig 50. example application diagram: dual btl master, single btl slave in i 2 c-bus mode . . . . . . . . . . . . 45 fig 51. package outline sot851-2 (hsop36) . . . . . . . . 46 fig 52. temperature profiles for large and small components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
nxp semiconductors tdf8599a i 2 c-bus controlled dual channel class-d power amplifier ? nxp b.v. 2013. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 2 may 2013 document identifier: tdf8599a please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 24. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 quick reference data . . . . . . . . . . . . . . . . . . . . . 2 5 ordering information . . . . . . . . . . . . . . . . . . . . . 2 6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 7.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 functional description . . . . . . . . . . . . . . . . . . . 5 8.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 8.2 mode selection . . . . . . . . . . . . . . . . . . . . . . . . . 6 8.3 pulse-width modulation frequency . . . . . . . . . . 7 8.3.1 master and slave mode selection . . . . . . . . . . . 7 8.3.2 spread spectrum mode (master mode) . . . . . . 8 8.3.3 frequency hopping (master mode). . . . . . . . . . 9 8.3.4 phase lock operation (slave mode) . . . . . . . . 10 8.4 operation mode selection. . . . . . . . . . . . . . . . 11 8.4.1 modulation mode . . . . . . . . . . . . . . . . . . . . . . 11 8.4.2 phase staggering (slave mode) . . . . . . . . . . . 13 8.4.3 parallel mode . . . . . . . . . . . . . . . . . . . . . . . . . 14 8.5 protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8.5.1 thermal foldback . . . . . . . . . . . . . . . . . . . . . . 15 8.5.2 overtemperat ure protection . . . . . . . . . . . . . . 15 8.5.3 overcurrent protection . . . . . . . . . . . . . . . . . . 15 8.5.4 window protection . . . . . . . . . . . . . . . . . . . . . 15 8.5.5 dc offset protection . . . . . . . . . . . . . . . . . . . . 16 8.5.6 supply voltages . . . . . . . . . . . . . . . . . . . . . . . 17 8.5.7 overview of protec tion circuits and amplifier states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8.6 diagnostic output . . . . . . . . . . . . . . . . . . . . . . 17 8.6.1 diagnostic table . . . . . . . . . . . . . . . . . . . . . . . 17 8.6.2 load identification (i 2 c-bus mode only) . . . . . 18 8.6.2.1 dc load detection . . . . . . . . . . . . . . . . . . . . . . 18 8.6.2.2 recommended st art-up sequence with dc load detection enabled . . . . . . . . . . . . . . . . . . 20 8.6.2.3 ac load detection . . . . . . . . . . . . . . . . . . . . . . 21 8.6.2.4 clip detection . . . . . . . . . . . . . . . . . . . . . . . . 21 8.6.3 start-up and shutdown sequence . . . . . . . . . . 22 9 i 2 c-bus specification . . . . . . . . . . . . . . . . . . . . 23 9.1 instruction bytes . . . . . . . . . . . . . . . . . . . . . . . 25 9.2 data bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 10 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 27 11 thermal characteristics . . . . . . . . . . . . . . . . . 28 12 static characteristics. . . . . . . . . . . . . . . . . . . . 28 12.1 switching characteristics . . . . . . . . . . . . . . . . 31 13 dynamic characteristics. . . . . . . . . . . . . . . . . 32 14 application information . . . . . . . . . . . . . . . . . 33 14.1 output power estimation (stereo mode) . . . . 33 14.2 output power estimation (parallel mode). . . . 34 14.3 output current limiting . . . . . . . . . . . . . . . . . . 35 14.4 speaker configuration and impedance. . . . . . 36 14.5 heat sink requirements . . . . . . . . . . . . . . . . . 36 14.6 curves measured in reference design . . . . . . 37 14.7 typical application schematics. . . . . . . . . . . . 42 15 package outline. . . . . . . . . . . . . . . . . . . . . . . . 46 16 handling information . . . . . . . . . . . . . . . . . . . 47 17 soldering of smd packages . . . . . . . . . . . . . . 47 17.1 introduction to soldering. . . . . . . . . . . . . . . . . 47 17.2 wave and reflow soldering. . . . . . . . . . . . . . . 47 17.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . 47 17.4 reflow soldering . . . . . . . . . . . . . . . . . . . . . . 48 18 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 49 19 revision history . . . . . . . . . . . . . . . . . . . . . . . 50 20 legal information . . . . . . . . . . . . . . . . . . . . . . 51 20.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 51 20.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 20.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 51 20.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 52 21 contact information . . . . . . . . . . . . . . . . . . . . 52 22 tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 23 figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 24 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

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